TOP: FPGA & HDL

Summer 2017
Credits 3 | Attributes Upper DivZZTL

Sections (2)

EE 4953 TOP: FPGA & HDL
2/17
Eratne, Savithra TTh 6:00-7:55 PM
EE 4953 TOP: FPGA
13/17
Patel, Parimal MW 6:00-7:55 PM
TTh
6 :00 PM– 7 :55 PM1h 55mEE 4953-02TTOP: FPGA & HDL
Eratne, Savithra
2 of 17
MW
6 :00 PM– 7 :55 PM1h 55mEE 4953-03TTOP: FPGA
Patel, Parimal 4.3
13 of 17

Instructors

Savithra Eratne
Parimal Patel
4.3
v0.8.4
GitHub
Status